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High-Performance UCIe Chiplet Interconnect IP

Chiplet Interconnect High Speed Low Latency PHY+Controller

UCIe IP includes PHY and Controller (with Adapter layer and Protocol layer), a complete die-to-die link solution compatible with UCIe specification, featuring high-bandwidth, low-power and low-latency.

  • Complete solution: PHY + Controller (Adapter layer & Protocol layer)

  • High bandwidth: data rate up to 32Gbps per pin, 16 lanes (16TX/16RX)

  • High reliability: BER<1e-15>

  • Protocol support: AXI/ACE/CHI/CXS over UCIe link

  • Testability: built-in self-test (BIST) for known good dies and package assembly yield

  • Advanced: side band channel, self-calibrating and training, EW (East/West) PHY direction, MCM 30mm, -40℃~125℃ junction temperature, 130um bump pitch

  • Process:4nm~28nm advanced nodes

  • Suitable for HPC, networking & storage, AIoT/ML accelerator, advanced package modules

Highlights

  • High Bandwidth

    32Gbps per pin, 16 lanes

  • Complete Solution

    PHY + Controller integrated

  • High Reliability

    BER<1e-15, CRC & retry

  • Protocol Compatible

    AXI/ACE/CHI/CXS supported

  • Advanced Process

    4nm~28nm

  • Low Latency

    High-speed die-to-die link

  • Self-Test & Training

    BIST, self-calibrating

Applications

  • HPC
    (High-Performance Computing)

  • Networking &
    Storage

  • AIoT/ML Accelerators
    Accelerator

  • Advanced
    Package Modules

  • Chiplet
    Integration

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