English

Foundation IP

Home Products IP Design

Standard Cell Library

Custom Standard Cell Library

Standard Cell Library High Performance Low Leakage Low Power

We provide standard cell library IP and custom development services across multiple process nodes from 7 nm to 350 nm, including specialty technologies such as RF-SOI, BCD, and TFT. Through circuit–layout co-optimization and multi-PVT-corner characterization, we optimize performance, power, and area for customer-specific applications.

  • Product Portfolio and Library Scale: Base and ECO standard cell libraries, as well as PMK power management cell libraries. Flexible library configurations ranging from 200 to 1,500 cells are supported, with customization based on the target process platform, design flow, and chip application requirements

  • Comprehensive Cell Portfolio: The portfolio covers combinational logic cells, including INV, BUF, NAND, NOR, XOR, XNOR, MUX, AOI, OAI; DFF, SDFF, Latch, and ICG sequential cells; TIEHI, TIELO, Filler, Tap Cellphysical cells; and Isolation Cells, Level Shifters, Power Switches, and Retention Flops power management cells

  • Multi-Architecture: Standard cell library designs with different cell heights and Vt options, enabling differentiated high-performance, general-purpose, and low-leakage libraries

  • Multi-Process Support: Solutions cover multiple process nodes from 7 nm to 350 nm, including standard cell architectures for FinFET platforms and specialty technologies such as RF-SOI, BCD, and TFT

  • PPA Optimization: Transistor sizing, circuit topology, and layout are co-optimized to meet application-specific performance, power, and area targets

  • Characterization Capabilities: Multi-PVT-corner characterization and Liberty model generation according to customer-defined signoff corners, supported by sufficient characterization-tool licenses and computing resources

  • Performance Advantages: Application-specific PPA optimization is achieved through the co-optimization of transistor sizing, circuit topology, and layout

  • Wide Applications: The libraries are suitable for AI, high-performance computing, automotive electronics, IoT, consumer electronics, and low-power wireless SoCs

We also support customized low-leakage libraries to reduce static power consumption. When integrated with ultra-low-power PMU/RF IP, they enable optimized low-power performance and form a complementary high-performance/low-power IP platform. Our process coverage includes 6.5T and 9T standard cell libraries for 28nm, 22nm, and FinFET technology platforms. These libraries have been adopted in low-power wireless SoC solutions, including BLE SoCs and Wi-Fi 6 & BLE combo SoCs. 

Highlights

  • Wide Node Coverage

    Covers multiple process nodes
    from 7 nm to 350 nm

  • Specialty Process Support

    Supports RF-SOI, BCD, and
    TFT specialty technologies

  • Multiple Cell Heights

    Supports libraries with
    different cell heights

  • Multi-Vt Library Design

    Enables high-performance and
    low-leakage libraries with
    multiple Vt options

  • Comprehensive Cell Portfolio

    Covers logic, sequential,
    physical, and power
    management cells

  • PPA Co-Optimization

    Co-optimizes circuits and
    layouts for target PPA

  • Signoff-Driven Characterization

    Performs multi-PVT characterization
    based on customer
    signoff corners

  • Low-Leakage Library and Lower Power IPs

    Customized low-leakage with
    low-power IP platform

  • Platform Synergy IP Solution

    Complementary IP platform with
    high-performance/low-power IPs
    and ultra-low-power PMU/RF IPs

Applications

  • AI chips

  • MCU

  • BLE SoC

  • Wi-Fi6 & BLE Combo SoC

  • low-power wireless connectivity chips

  • wearable device controllers

Contact TOP

Log in

Forgot your password?
Log in
Not a member? Sign up

Get verification code

 
Log in
Not a member? Sign up