Advanced PDK Verification Platform


PQLab is an advanced PDK (Process Design Kit) verification platform. As the semiconductor manufacturing technology continues scaling down to smaller geometries, PDK complexity increases rapidly. PDK validation is much more complicated than ever before and takes time.
Primarius developed PQLab as a complete solution based on years of experience in advanced PDK development and verification to address this challenge. PQLab is an automated QA software for PDKs, featuring a multitude of qualification mechanisms of PDK integrity, including technology files, PCell CDF, PCell physical verification (DRC & LVS), and SPICE models. PQLab supports PDK verification from 0.35um to 22nm for the planar process and from 16nm to 5nm FinFET process, covering the applications in digital logic, analog, high voltage, and RF circuits. PQLab helps foundries'PDK engineers ensure PDK quality. It enables IC designers to easily analyze and qualify foundry PDKs and benchmark between different PDK versions and design flows.


Key Advantage

Versatility: Supports mainstream foundries' PDK format and EDA tools


Supports PCell, DRC/LVS, simulation and technology file validation

Supports performance benchmarks between different PDK versions and various combination of different models, LVS, and PEX

Automation: Highly - integrated automation PDK QA environment

Efficiency: Built-in pattern generation module for each PDK component

Flexibility:Support test pattern user customization 

Reusability:Existing PDK QA setting could be reused in future project  




  • Test pattern generation automation

-- Automatically generates the test patterns for DRC, LVS, CDF and other PDK components

Supports CDF verification

-- CDF Spec, CDF Callbacks ,CDF Parameter and SPICE Model parameter consistency inspection

  • Supports DRC/LVS verification

-- Intelligently auto-generates the minimal set of the DRC and LVS inspection test patterns to ensure correct PDK functionality for any PCell parameter combination

  • Supports comprehensive simulation

-- Ensure the PDK output consistency through automatic comparison between pre-layout and postlayout simulations

  • Supports comparison of the results from different combinations of SPICE model, LVS and PEX
  • Supports DC OP back-annotation function verification Supports Pcell input variable function verification


Foundry process development

Foundry PDK development and verification

Fabless & IP vendor evaluation and verification of foundries' process

 Application Example