In analog circuit design, the parametric cell library (PCell) as an important component of the PDK (semiconductor process design kit) has become an indispensable part of the entire design process. With the rapid development of semiconductor technology, the increasingly complex structure of advanced semiconductor devices makes the development process of PCell more challenging. PCellLab is an automated development platform for PCell. The platform has complete PCell development functions and advanced technology. PCell code can be automatically generated according to the process and design parameters input by the use. It also reserves open interfaces for users for special processes and special needs, and supports users to customize the development of input templates according to their own process characteristics, supporting PDK developers to quickly complete development work efficiently and with high quality.
- Versatility：Support bulk silicon planar process, SOI process, BCD process, FinFET process, etc.
- Completeness：Supports automatic generation of PCell components such as Symbol, CDF, Callback, View, etc.
- Automation：Highly integrated automated development process
- Efficiency：Rich and comprehensive PCell development functions improve development efficiency significantly
- Flexibility：Combination of standardized functions and customized functions to support user customization
- Easy to use：The GUI is friendly and supports mathematical expressions input, greatly shorten the development learning curve and reduce development difficulty.
- Semiconductor process development
- Foundry PDK development
- Fabless/IP vendor PCell development
- Support PCell automatic generation： Use simple and flexible GUI to input data, intelligently generate CDF files in PCell, Design Rule related information, Callback functions and Skill layout scripts, etc., and support the simultaneous generation of single or multiple items
- Support multi-mode PCell Library compilation： Support CDF, Callback, layout independent or multiple simultaneous build mode Support single or multi-layer Metal Option at the same time
- Support update function： Flexible update of single or multiple PCell CDF parameter information, simulation information, Design rule, Callback and other information, and automatically extract the differences
- Support customized functions： Support automatic loading of customized functions
- Supports PCell creation of Hierarchy structure: Support the compilation of simple circuit-level Hierarchy structure PCell
Automatically generate layout from circuit schematic