Introduction

NavisPro provides RTL design-based planning solution that predicts and prevents implementation issues commonly found in physical implementation. NavisPro also enables designers to minimize unnecessary design iterations and shortens the time to market their SoC designs. This unique solution for hierarchical floorplanning addresses the complexity problem of SoC design via intelligent partitioning of the full-chip into many blocks or sub-systems. For example, in modern SoC designs, many processors are used in a single chip. Each sub-system layout is implemented independently. In the NavisPro environment, chip partitioning includes physical hierarchical partitions of the design and the pin placements of each sub-system. The pin placement of a sub-system is one of the critical constraints of sub-system layout, and it determines the extent of full-chip routing congestion. Accurate estimation of the bus interconnect timing between sub-systems is critical for timing closure. Estimation of the interface net timing across the design hierarchy is a very useful feature for full-chip timing analysis.

Key Advantage

• Chip system architecting
• Minimization of chip area
• Faster design refinement
• Efficient system partitioning
• Optimization of system specification
• High QoR of physical implementation

Applications

Specifications

 Constraints driven RTL based floorplanning

• Components placement & area estimation
• Automatic & manual pin assignment
• Global routing congestion analysis
• Bus interconnect exploration
• Interconnect delay estimation
• Automatic pipelining placement
• Bump array structuring

Flexible top-down & bottom-up floorplanning Design & constraints exploration

• Low power intent exploration
• Clock structure exploration
• RTL design exploration