Hierarchical SoC Design Planning Solution



NavisPro is a power and timing aware RTL design planning solution which predicts and prevents implementation issues commonly found in physical implementation. NavisPro enables the user to find the optimal number of power pads and their locations to meet the target IR-drop and Simultaneous Switching Noise (SSN) margin in the early design stage. NavisPro also enables designers to minimize the unnecessary design iterations and to shorten the time to market of their SoC designs. This unique solution for hierarchical floorplanning addresses the complexity problem of SoC design via intelligent partitioning of the full chip into many blocks, or sub-systems. As an example, In modern SoC designs, many processors are used in a single chip. Each sub-subsystem layout is implemented independently. In the NavisPro environment, chip partitioning includes physical hierarchical partitions of the design and the pin placements of each sub-system. The pin placement of a sub-system is one of the critical constraints of sub-system layout and it determines the extent of full-chip routing congestion. Accurate estimation of the bus interconnect timing between sub-systems is critical for timing closure. Estimation of the interface net timing across the design hierarchy is a very useful feature for full chip timing analysis.


Key Advantage


  • Constraint driven RTL floorplanning
  • Feasibility analysis of package design
  • Fast design iteration


  • Visualized RTL design exploration & debugging
  • Visualization of the clock tree structure and clock design rule check
  • Validation and edition of power constraints with graphical debugging environment
  • Design constraints management in early design stage


Floorplanning & feasibility analysis of SoC design in RTL design stage

IO pad configuration with bump pads structuring for flip-chip style design

RTL & gate-level cell-based digital (logic) design 



  • Hierarchical Floorplanning

  • Constraint driven RTL floorplanning

-- Efficient pin assignment

-- Bus interconnect analysis

-- Interconnect net delay estimation

-- Routing congestion analysis

-- Bump array generation

  • With PadOptima optional

-- Optimal pad configuration

-- RDL routing feasibility analysis


  • RTL design exploration with multi-level schematic

  • Area estimation

  • Clock structure analysis

  • Low power design intent analysis
  • Analytic power estimation

 Application Example   

Constraint Driven Floorplanning

Automatic / Manual Pin Assignment

Routing Congestion Estimation


Bus Interconnect Planning


Hierarchical Floorplanning