NanoYield™ is a unique design-for-yield platform that, for the first time, integrates all the key components from a single vendor: (1) advanced device modeling, (2) a parallel SPICE simulation engine and (3) hardware-validated statistical analysis algorithms.
NanoYield significantly increases statistical circuit analysis speeds with its superior parallelization technology and highly efficient and accurate statistical algorithms. This enables designers to run yield predication as well as yield-PPA (power, performance and area) trade-off for memory, digital and analog circuits. Primarius offers an integrated GUI-based DFY (design for yield) environment – Nano Design Environment (NDE) - to assist designers in running variation analysis, predict yield, in addition to guiding their designs for optimum yield and PPA.
Full integration: Advanced modeling, built-in SPICE engine and high efficient statistical algorithms
Superior speed: Fast PVT (process, voltage, and temperature)-3-20X; fast Monte Carlo - 10-100X+; advanced High Sigma-103-105X+
Scalable parallelization: Near-linear scaling on both private farm or public clouds
High accuracy: Silicon validation at 14nm, 7nm & 5nm
Simplified licensing: Most economic parallelization licensing model
4-7σ yield analysis for memory and standard cell designs
Fast Monte Carlo analysis for analog and digital block designs
Fast PVT analysis for analog and digital block designs
Supports Hspice and Spectre netlist formats
Full SPICE analysis features (same as NanoSpice)
Full SPICE model support (same as NanoSpice)
Full PVT and fast PVT analysis
Monte Carlo analysis
High Sigma analysis (4-7σ+): 20K+ variables
System High Sigma analysis for full chip yield analysis
Rich yield prediction and statistical circuit analysis functions, e.g., sensitivity analysis, parameter sweeping, etc.
Powerful GUI-based circuit analysis features through Nano Design Environment
64bit Redhat Enterprise V5.x, V6.x, V7.x, V8.x ;
64bit CentOS V5.x, V6.x, V7.x, V8.x
Multi-core server or computer farm