Introduction
NanoSpice Giga™ is the industry's first and only GigaSpice, designed for accurate verification and signoff of advanced memory designs, an area where FastSPICE has fundamental limitations. With its innovative parallel simulation engine built upon big data architecture, NanoSpice Giga can effectively handle billion-elements designs. The capability makes it ideally suited for verification and signoff of memory, custom or semi-custom digital circuits, and full-chip designs. In comparison to FastSPICE, NanoSpice Giga uses a pure SPICE engine to offer substantially higher accuracy for power, leakage, timing and noise characterizations and verifications. Its superior parallelization technologies deliver faster simulation speed without sacrificing accuracy. NanoSpice Giga directly replaces FastSPICE and serves as the golden signoff simulator for memory IP and full chip verifications.
Key Benefits
Superior accuracy: Pure SPICE accuracy with DC convergence, for accurate power/leakage/timing/noise
Giga-scale capacity: Ability to handles real full chip verification and signoff (>109 elements)
High performance: Faster and scalable to 32+ threads. Specially optimized for FinFET/FD-SOI models
No FastSPICE options: no tuning, removes guesswork from FastSPICE
Foundry validated accuracy: 14/7/5nm FinFET and 28nm FD-SOI ready
Applications
Embedded memory IP verification
Full chip memory IC verification (DRAM,SRAM,Flash)
Memory characterization
Custom or semi-custom digital: clock tree, critical path analysis
Design Flow Integration
Drop-in replacement for accurate power/leakage/timing/noise verification and signoff
Plug and run without FastSPICE options and tuning
Specifications
Supports Hspice and Spectre netlist formats
Supports standard output formats for data analysis: FSDB, PSFASCII, SPICEASCII, ASCII, etc
Unique transient output format - nwf, reduce 2x+ file size
Full SPICE analysis features: OP, DC, AC, Noise, Tran, Info, Sweep, Alter, Stability, FFT, Bisection, Pole-Zero, DC Match, AC Match, Monte Carlo, PVT, Tran Noise, etc
Supports all public domain models, user-defined models
MOSFET models include BSIM3, BSIM4, BSIM6, BSIMSOI, BSIM-CMG, BSIM-IMG, UTSOI, PSP, HSIM2 , HiSIM_HV, MOS9, MOS11
Bipolar models include Gummel-Poon, VBIC, HICUM, Mextram
Diode, JFET, MESFET, RLC, TFT, TSMC model interface (TMI)
Supports Verilog-A and behavioral sources
Supports VEC and VCD stimulus files
Supports SPEF, DSPF, DPF back-annotation
Supports IBIS model, S-parameter and transmission line, etc
Supports Verilog co-simulation
Platform Supported
64bit Redhat Enterprise V5.x, V6.x, V7.x, V8.x ;
64bit CentOS V5.x, V6.x, V7.x, V8.x
Multi-core server or computer farm
Cloud