bg
title-img

NanoSpice Pro

Dual Solver & High Performance FastSPICE

Introduction

NanoSpice Pro is a revolutionary high-performance and highcapacity FastSPICE circuit simulator. Its dual-solver engine boosts simulation throughput of all modern complex designs including memory (DRAM, SRAM, Flash, MRAM), FPGA, custom digital and SoC circuits. 

With the breakthrough FastSPICE algorithm, intelligent topology recognition and automatic partition technology, NanoSpice Pro delivers superior performance and capacity to address advanced node verification challenges. Adaptive dual-solver technology ensures superior analog accuracy and digital performance for mixed-signal designs, benefiting from a seamless integration of the state-of-the-art digital engine and the giga-scale analog engine. 

NanoSpice Pro provides a unique one-stop memory simulation solution to meet all needs from memory cell design, memory array and compiler verification, memory characterization, and fullchip verification with up to 10X+ performance increase over other commercial simulators.  

 


Key Advantage

Breakthrough algorithm:Intelligent topology recognition and automatic partitioning 

Higher capacity :Up to 10X+ faster simulation throughput 

Advanced RC reduction and fast yet accurate model evaluation 

Adaptive dual-solver :Superior analog accuracy and digital performance 

High Performance Performance scales linearly with 32+ multi-core simulations

Unique one-stop memory simulation solution

Applications

Memory IC dynamic power dissipation and timing simulation 

Memory characterization and function verification 

SoC full chip fast timing and functional verification 

Specifications

  • Supports Hspice and Spectre netlist formats 
  • Supports all public domain models, user-defined models 

-- MOSFET: BSIM3, BSIM4, BSIM-BULK, BSIM-IMG, BSIM-CMG, BSIM-SOI, LETI-UTSOI, PSP, HiSIM2, HiSIM_HV, EKV3 

-- BJT: MAXTRAM, VBIC, HICUM; TFT: a-Si TFT, poly-Si TFT

-- Diode: JUNCAP, JUNCAP200, DIODE_CMC; Varactor: MOSVAR 

-- Resistor: R2_CMC, R3_CMC; HEMT: ASM-HEMT; JFET/MESFET; TMI;Custom PMI; Bsource 

  • Supports S-parameter, Transmission line (W element, T element), IBIS model 
  • Supports standard output formats for data analysis: FSDB, PSFASCII, SPICEASCII, ASCII, etc 
  • Unique transient output format - NWF, reduce 2x+ file size
  • Supports VEC and VCD stimulus files 
  • Supports SPEF, DSPF, DPF back-annotation 
  • Supports Verilog co-simulation
  • Drop-in replacement of any FastSPICE in existing design flows  
  • Support public cloud platform, hybrid cloud and private cloud

 Application Example