A standard cell library is essential for chip design, including circuit design, layout design, and characterization. The standard cell library characterization needs many simulations, model extraction, and verification, which occupies more than one-third of the time in developing a standard cell library. Therefore, improving the efficiency of the standard cell library characterization is the key to shortening the development cycle. With the shrinking of process nodes, the design complexity of the chip increases day by day. Under the advanced technology, the introduction of many signoff process corners and the ultra-low voltage design of near-threshold voltage put forward higher requirements for the feature extraction of cell libraries, such as timing, power consumption, noise, and statistical variation. So, the amount of simulation calculation increases exponentially, which has become the bottleneck of digital chip design.
NanoCell is a fast, accurate, and easy-to-use standard cell library characterization EDA tool. It adopts intelligent analysis algorithms to analyze and extract arcs and functionalities of the cells. By leveraging advanced distributed computation technology and a powerful built- in NanoSpice engine, it accurately and efficiently simulates and builds the timing, power consumption, noise, and other characteristics of standard cells. Also, NanoCell provides user-friendly and easy-to-use interfaces to help users shorten product development cycles.