Standard cell library is an important basis for chip design, including circuit design, layout design and characterization extraction. The standard cell library characterization needs a lot of simulation, model extraction and verification, which occupies more than one-third of the time in the development of standard cell library. Therefore, improving the efficiency of standard cell library characterization is the key to shorten the development cycle. With the improvement of process nodes, the design complexity of chip increases day by day. Under the advanced technology, the introduction of a large number of signoff process angles and the ultra-low voltage design of near threshold voltage put forward higher requirements for the feature extraction of cell library, such as timing, power consumption, noise and statistical variation, so that the amount of simulation calculation increases exponentially, which has become the bottleneck of digital chip design.
NanoCell is a fast, accurate and easy-to-use standard cell library characterization EDA tool. Through the built in NanoSpice simulator, it adopts advanced distributed parallel architecture technology and cell circuit analysis and extraction algorithm to accurately and efficiently simulate and extract the timing, power consumption, noise and other characteristics of cell circuits, providing friendly and easy-to-use interfaces, help users shorten the product development cycle.