- Prevent inconsistency between library views
- Achieve integrity of Liberty
- Datasheet generation
- LEF generation from the physical layout
As the semiconductor process technology node continues to scale, standard cell library providers are facing challenges associated with ever-increasing library complexity, as driven by the chip design process. Consistency and validity of heterogenous cell libraries must be guaranteed to eliminate unnecessary design schedule delays.
LibWiz provides a solution for trend analysis between PVT corners to ensure library integrity. Based on these analysis results, LibWiz also supports datasheet generation for use by chip designers.In addition, LibWiz supports seamless abstract layout generation from full-custom physical layout design to reduce design costs.
Standard cell library views are specified as Verilog HDL, OASIS (GDS-II), SPICE, Liberty and LEF. Because It is essential to keep consistency of all views. LibWiz utilizes a cross-check methodology to extract common parameters in each cell library, and then checks consistency between libraries.
LibWiz checks formal syntax and semantics of all libraries, and supports a sequential process to check function equivalence and all properties such as cell area, pin list, pin property as direction, and timing arcs. LibWiz features a user-friendly GUI environment with cross-probing functions, and generates html, pdf and txt format file for convenient analysis and post-processing of data.
Standard cell & IO library design
Analog/Mixed-signal IP & custom layout design
checking the consistency of libraries