- Prevent inconsistency between library views
- Achieve integrity of Liberty
- Datasheet generation
- LEF generation from the physical layout
As the process technology node of semiconductors is getting sophisticated and intricated, the library kit provider delivers various and complicated standard cell libraries according to requirements in the chip design process. Consistency and validity between heterogenous libraries must be guaranteed to remove the unnecessary designing delay.
LibWiz provides a solution for trend analysis between PVT corners to ensure integrity. Based on this analysis result, it also supports datasheet generation that must be provided to chip designers using them as well.
In addition, LibWiz supports seamless abstract layout generation from full-custom physical layout design to reduce designing costs.
Standard cell library is specified as Verilog HDL, OASIS (GDS-II), SPICE, Liberty and LEF for each purpose.It is essential to keep the consistency of all libraries. LibWiz adopts cross-check methodology with extracting common denominator in each cell library, and then, checking consistency between libraries.
LibWiz checks formal syntax and semantic of all libraries basically, it also supports sequence process to check function equivalance and each properties such as cell area, pin list, pin property as direction, and timing arc. Based on analyzed result as above, LibWiz provides user-friendly GUI environment with cross-probing function, and generates html, pdf and txt format file for convenient analysis.
Standard cell & IO library design
Analog/Mixed-signal IP & custom layout design
checking the consistency of libraries